In data communication, data are often transferred from one circuit to another circuit for processing. To capture a data signal, a data capture circuit is used. The data capture circuit normally uses a clock signal to capture the data signal. The clock signal can be a system clock signal or an internal clock signal generated by a clock generator.
FIG. 1A is a block diagram illustrating one traditional clock and data signal relationship of a capture circuit. In this method, the system clock signal is edge aligned with the captured data signal while the capture clock signal is center aligned with the data eye. In other terms, the capture clock signal is 90 degrees out of phase or one-fourth clock cycle delayed from the system clock signal and is center aligned with the data signal.
FIG. 1B illustrates possible data and clock paths of a capture circuit in a memory device or a memory controller. In this circuit, a data latch (DQ latch) uses a capture clock signal (CAPCLK) to capture an internal data signal (Din). The Din signal is a delayed version of an external data signal (DQ), which travels on a data path including a data pad (DQ pad) and a data receiver and driver (D Rx). The data path has a delay indicated by dly-DQ. The CAPCLK is provided by a clock distribution tree as a delayed version of an output clock signal (CLKout). The clock distribution tree has a delay indicated by dly-CLK. The CLKout clock signal is generated by a clock generator based on a system clock or an external clock signal (XCLK). The XCLK signal is edge aligned with the DQ signal.
From the data and clock paths of FIG. 1B, even if the CLKout signal is 90 degrees out of phase with the XCLK signal, the capture clock signal, CAPCLK, may not be center aligned with the Din data signal because of variations in delays of the dly-DQ and dly-CLK.
Conventionally, different techniques are used to match the delays of the data and clock paths, such as the dly-DQ and dly-CLK, to center align the capture clock signal to the data signal. A common characteristic of these techniques is adding delay elements to the data or clock path or both. The delay elements are then manually tuned in as an attempt to compensate the variations in delays between the clock and data paths. In some cases, tuning the delay elements may not provide satisfactory level of accuracy. Thus, the clock and data signals may not accurately be aligned for some devices, especially for high speed devices such as new generations of memory devices.
There is a need for another technique to generate a capture clock signal that is accurately center aligned with the data signal.